A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology.

Hexagonal Binary Decision Diagram Quantum Logic Circuits Using Schottky In-Plane and Wrap Gate Control of GaAs and InGaAs Nanowires

Previous quantum device research has been done on discrete device levels and lacks a clear vision for high density integration. This paper proposes a new, simple and realistic approach for quantum large scale integrated circuits (QLSIs) where a binary-decision diagram (BDD) logic architecture is implemented by BDD node devices based on quantum wire transistors (QWTrs) and single electron transi...

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...

Properties of a GaAs Single Electron Path Switching Node Device Using a Single Quantum Dot for Hexagonal BDD Quantum Circuits

Abstract. A new single electron (SE) binary-decision diagram (BDD) node device having a single quantum dot connected to three nanowire branches through tunnel barriers was fabricated using etched AlGaAs/GaAs nanowires and nanometer-sized Schottky wrap gates (WPGs), and their operation was characterized experimentally, for the hexagonal BDD quantum circuit. Fabricated devices showed clear and st...

Word Level Symbolic Model Checking A New Approach for Verifying Arithmetic Circuits

The highly-publicized division error in the Pentium has emphasized the importance of formal verification of arithmetic operations. Symbolic model checking techniques based on binary decision diagrams (BDDs) have been successful in verifying control logic. However, lack of proper representation for functions that map boolean vectors into integers has prevented this technique from being used for ...